Design Verification Engr

About TI
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world's brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We're committed to building a better future - from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us - change the world, love your job!

About the Job
  • Join a team developing state of the art phase locked loops (PLLs) for clock timing solutions used by communications and computing systems in various markets.
  • Create and execute a thorough pre-silicon verification plan to ensure first pass success of mixed-signal IC products.
  • Understand and evaluate system-level use-cases and re-create these in simulation.
  • Implement mixed-signal test-benches to apply stimulus and checks to verify device behavior
  • Create SystemVerilog functional coverage models of mixed-signal circuits for voltages, currents, real numbers, integers, and traditional digital functional coverage.
  • Work with complex mixed-signal semiconductor chip designs.
  • Create behavioral models of analog circuits and verifying closed-loop simulation with digital design and analog behavioral models.
  • Work with design and systems teams to close bugs as they arise.
  • Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
  • Develop constrained-random stimulus and auto-checking verification environments, especially constrained random analog stimulus.
  • This role also requires collaboration with other DV teams and functions in the business unit to help improve the DV practices and execution efficiencies across the business unit. This position provides high visibility both within and outside the group.


Minimum Requirements
  • Bachelor's degree in electrical engineering (BSEE)
  • Minimum of 3 years of experience in Mixed Signal Design Verification and/or Analog or Digital Design. MSEE may be considered as equivalent to the needed years of experience.
  • This position is in Federal Way. The successful candidate is living in that area or is willing to relocate.


Preferred Qualifications
  • UVM (Universal Verification Methodology) certification or training
  • Verification planning, development of verification/test plans using system/block/sub-system specs/datasheet
  • Scripting and automation using Unix/Linux shell, PERL, Python, C or other similar languages
  • SystemVerilog, Verilog RTL, Verilog-AMS and Verilog-A, functional and code coverage, constrained-random stimulus, and assertions
  • Analog circuit design understanding, transient, DC, AC simulation and Monte Carlo analysis
  • Familiar with PLLs and/or general control theory
  • Cadence Virtuoso, Spectre circuit simulator, Incisive and AMS simulators
  • Strong verbal and written communication skills
  • Ability to work in teams and collaborate effectively with people in different functions
  • Ability to take the initiative and drive for results
  • Strong time management skills that enable on-time project delivery
  • Good listener and excellent verbal and written communication skills

To be considered for this position, please apply.

If you are interested in this position, please apply to this requisition.

Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to protected characteristics, including race, color, religion, sex, national origin, disability, veteran status, sexual orientation, gender identity or age.