Layout Designer - Linear & Low Dropout Regulators

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About TI
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world's brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We're committed to building a better future - from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us - change the world, love your job!

Texas Instruments will not sponsor job applicants for visas or work authorization for this position.

As a Senior Layout Engineer you are expected to:
  • Lead and/or Own all the aspects pertaining to the layout of a block/device in the field of power management IC design ( LDO's), this includes but is not limited to schedule, planning, tracking and communicating the layout milestones, floorplan, power-plan, constraint management, layout, verification, extraction, drive and attend reviews, interface with assembly team for package requirements, interface with the fab. for tapeout/PG,
  • Develop individual block layout specification based on top level layout requirements.
  • Guide the design team on layout DFM constraints like matching, parasitics, EM, ESD, Latch-up, etc.
  • Aggressively drive area reduction, maximize re-use
  • Aggressively drive productivity improvement initiatives through automation, flow-methodologies improvements, checklists etc.
  • Push the envelope on fab. process capabilities by working with process team for waivers, customizing verification rule decks and/or process flavors
  • Push the envelope on assembly capabilities by working with packing team for new package development, optimize layout to fit in to multiple packages
  • Coach/Mentor junior team members




Minimum requirements
  • High School Diploma or GED or technical program
  • 5+ years of experience in IC Layout

Preferred qualifications:
  • Associates degree in Electronics-related field
  • Experience and strong skills with Cadence Tools: Layout XL, Annotation Browser, Connectivity Driven Layout, Assura, PVS
  • Full custom analog block-level and chip-level layout/verification
  • Understanding and implementation of good layout practices for matching, low noise, reduced parasitic coupling, area savings, etc.
  • Good understanding of semiconductor technology, process, and device physics
  • Unix and Cadence database management skills
  • Ability to take the initiative and drive for results
  • Strong time management skills that enable on-time project delivery
  • Ability to work well in teams and collaborate effectively across locations
  • Demonstrated ability to build strong, influential relationships
  • Good listener and excellent verbal and written communication skills


Successful applicants for this position must be fully vaccinated against COVID-19 as a condition of employment. Vaccine verification will be required on your start date unless an exemption has been approved by TI as a medical or religious accommodation.

If you are interested in this position, please apply to this requisition.

Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws.