Design Verification Engineer-Custom

About TI

Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future - from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.

About the Job:

As a Digital Design Verification Engineer you will be responsible for the below duties:

• Lead the pre-silicon verification of complex digital blocks for incorporation into mixed-signal products.
• Create digital verification plans using datasheets, inputs from engineers/customers, and working closely with system and design engineers.
• Implement digital test-benches in SystemVerilog (or UVM) to apply constrained random stimulus and checks.
• Implement Systemverilog Assertions (SVA) to check digital DUT behavior.

• Provide periodic updates on DV status to project participants, management, and customers.
• Work with design and systems teams to close bugs as they arise.
• Drive new and improved methodologies where needed, work with the EDA team to upgrade tools and flows.
• Review the digital design to provide guidance on Design for Verification architecture and features.

Minimum Qualifications:
Bachelors of Electrical Engineering or related field of study

5+ years of design verification experience

Preferred Qualifications:

• Strong understanding and hands on experience with:
• Leading verification of complex digital blocks

• Experience working in mixed signal design environments
• Creating top-level verification plans in collaboration with internal engineers and external customers
• Creating schedules, resource plans, and executing DV of a digital design from concept to tape-out
• Verilog and Systemverilog
• Advanced verification methodologies such as UVM, eRM, VMM, or VERA
• Creating constrained-random stimulus and coverage based auto-checking verification environments
• Bug tracking, functional coverage, RTL code coverage
• Comfortable debugging and verifying gate level with annotate SDF.

Management/Organizational Skills:
• Ability to build strong, trusting internal and external relationships.
• Ability to work well with cross-functional teams.
• Project management, time management, multi-tasking, problem solving and communication (written and oral).
• Must possess the natural ability to motivate and drive accountability within the team.
• Must have a strong drive to develop talent within the team.
• Will be seen as the DV expert in the team. Knowledge sharing is critical.
• Digital Design Experience

• Assertion methodology and formal verification

• Analog transistor-level design or simulation experience
• Understanding of the full digital flow from RTL, synthesis, place-and-route, timing closure, SPEF, SDF, and Gate-Level Sims
• Experience with I2C, SPI, EMV, USB, AHB, or MIPI protocols

Successful applicants for this position must be fully vaccinated against COVID-19 as a condition of employment. Vaccine verification will be required on your start date unless an exemption has been approved by TI as a medical or religious accommodation.

If you are interested in this position, please apply to this requisition.

Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws.