Digital Design Verification Engineer - Processors

About TI

Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!

About the Job

As a member of the Embedded Processors team, you will be working on state-of-the-art processors targeted at the most exciting and growing automotive and industrial markets such as advanced driver assists systems (ADAS), vehicle gateways and zone controllers, building automation, and motor control, and factory automation & control. These products push the boundaries of technology integrating deep learning accelerators, ARM/RISC-V compute cores, vision analytics, networking, security, multimedia, and a rich set of the latest peripherals for memory storage and communication.

You will define design verification methodologies, tools, and flows to ensure that differentiated IP meets all functional and quality specifications and be expected to learn the functionality of the IP and the system context to build comprehensive verification test plans and milestone-based schedules. This role offers the opportunity to learn the complex SoC development process and interact with various functional teams spanning systems, design, software, and applications.

Responsibilities may include, but are not limited to:

• Promote advance verification methodology of complex digital logic using UVM testbench for block level through full system
• Architect, develop and drive module and system-level test strategies, verification plans, testbenches, functional models and test cases
• Create, execute, enhance and debug coverage-driven, constrained-random stimulus
• In depth knowledge of verification principles using UVM and System Verilog
• Define and implement functional coverage and drive coverage closure
• Extensive experience debugging complex designs to identify root cause of problems
• Collaborate across verification teams on reuse of components
• May include verification of SOC in an emulation environment and post silicon verification/characterization

Minimum Requirements:

• Bachelor’s degree in Electrical/Computer Engineering, Computer Science, or related field of study
• 3+ years of experience in design verification, System Verilog, and UVM

Preferred Qualifications:

• Must know Verilog language
• Experience with scripting languages such as Perl and Python
• Deep working knowledge of EDA verification tools
• Preferred to have experience with C-level and ASM level programming/debug
• Familiarity with Formal verification methodology/tool preferred
• Experience with bus-protocol (i.e. AXI, OCP) and/or Networking/Ethernet protocol verification would be preferred