Digital IC Design Engineer-DLP

About TI
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!

About the job
In this position, your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.

As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.

This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.

In this role, you’ll be responsible for digital custom design of high speed I/O Path, memory, used in integrated mixed signal DMD ICs for consumer display applications. Specific responsibilities include:

• Definition, design, layout, and evaluation of circuit building blocks in LBC technologies.
• Knowledge of RTL flow from synthesis to PnR and ability to write constraints to close timing at high speeds
• Work with design teams on internal supply and signal integrity analysis: Package /die IR prediction and optimization of supply decoupling
• Work with IC layout team to optimize post-layout parasitics for on-die routing for >1.6GHz signals
• Development of gate level design as well as behavioral models for standard digital cells
• Creating models and collateral IP to support a synthesizable design flow
• Manage and develop required minimum best practices for digital design
• Automate of design flows; Knowledge of Skill coding in Cadence is plus
• Top level verification and connectivity of circuit subsystems design
• Work in cross-functional teams as a technical contributor
• Work in low power applications

Minimum requirements:
• 5+ years of relevant experience

• Bachelors degree in electrical engineering or related field of study
• A thorough understanding of digital logic design
• Familiarity with the Verilog language and simulators
• A good understanding of analog functionality and exposure to analog IC design methods
• Ability to solve problems using a systematic approach

Preferred qualifications:
• Demonstrated strong analytical and problem solving skills
• Strong verbal and written communication skills
• Ability to work in teams and collaborate effectively with people in different functions
• Strong time management skills that enable on-time project delivery
• Demonstrated ability to build strong, influential relationships
• Ability to work effectively in a fast-paced and rapidly changing environment
• Ability to take the initiative and drive for results